1. Field of the Invention
This invention is in the field of methods of forming raised input/output terminals on the top, or exposed, surfaces of semiconductor elements while the elements are still integral with the single crystal silicon wafer on which the elements are formed. A photolithographic process using a layer of heat resistant photoresist material is used to form masks through which barrier metal layers of each I/O terminal are deposited on exposed portions of the metalization layers of such elements. The same photolithographic process is used to form a mask through which a layer of solder is then deposited on the exposed surface of the barrier metal layer of each terminal and an area of the passivation layer surrounding the barrier metal. The solder is melted which results in the I/O terminals having a substantially spherical exposed surface.
2. Description of the Prior Art
Some integrated circuits (IC) chips or elements are provided with raised I/O terminals, or I/O bumps. These I/O terminals are made of various conductive metals such as gold or tin/lead solder, for example. The I/O bumps project a substantial distance above the passivation layer of such elements on the order of 15-26 micrometers, or microns, or 1-2 mils. Semiconductor elements, including those with I/O bumps are generally produced starting with a wafer cut from a single crystal of essentially pure silicon. The I/O bumps of each IC element are formed while the elements are still an integral part of the wafer.
Heretofor, raised solder I/O bumps have been formed after the conventional step of etching holes, or vias, through the passivation layer has been completed to provide access to the metalization layer, commonly aluminum, which is in direct contact with the silicon crystal. The metalization layer underlies a passivation layer of silicon dioxide SiO.sub.2 or silicon nitride Si.sub.3 N.sub.4, for example. Barrier metal layers typically consisting of layers of chromium, copper and gold are deposited by conventional vapor deposition, or sputtering techniques, on the areas of the metalization layer exposed through the via openings. The conventional process for depositing metals on a semiconductor substrate uses a metal mask in which the apertures will have diameters slightly greater than the diameters of the vias by an amount substantially in a range of 2 mils (0.002 inches). A layer of tin lead is then deposited on the barrier metal layers in contact with the metalization layers and the exposed areas of the passivation layer through apertures in a metal mask which apertures are oversized relative to the barrier metal layers previously deposited by about 4 mils. The tin/lead solder is melted and the surface tension of the liquid solder draws the solder overlying the barrier metal layer into a compact mass to form a tin/lead raised I/O terminal or bump, the exposed surfaces of which are substantially spherical.
A major problem encountered when using apertured masks which are typically made from molybdenum arises as the diameters of the semiconductor wafers increased from approximately 1 inch in the early 1960s to 4 inches at the present time with no limit on the maximum diameter of such wafers yet discernible. The differences in the thermal coefficients of expansion of silicon and molybdenum is such as to cause the apertures in the metal mask to move out of alignment, or registry, with the vias previously etched in the passivation layers where the I/O bumps are to be formed to a degree that is not acceptable if semiconductor devices of acceptable quality and at an acceptable cost are to be produced. The misalignment between the openings in a mask and the via openings of the elements of the wafer leads to metalurgical failures, adhesion failures of the barrier metal to the passivation layer, and the formation of poor, or no, electrical contacts with the underlying metalization layer of the elements.
In addition the high temperature associated in vapor depositing or sputtering metals, on IC wafers through a metal mask can cause the metal mask to buckle with the result that excess metal can be deposited which excess metal can result in electrical shorts between I/O terminals, for example. Further since the metal masks must be cleaned after each use, they are subject to damage as the result of being subjected to such cleaning by removal of metal from the masks, by etching, for example, which renders the masks no longer serviceable. As a result the useful lives of such masks are relatively short and their cost, approximately $100/each increases the cost of producing integrated circuit chips having raised I/O bumps.